instruction pipeline
英 [ɪnˈstrʌkʃn ˈpaɪplaɪn]
美 [ɪnˈstrʌkʃn ˈpaɪplaɪn]
网络 指令流水线; 指令管线
双语例句
- If the first instruction in this fetch group is an even pipeline instruction and the second one is an odd pipeline instruction, they can both be issued simultaneously.
如果这个取出组中的第一条指令是一条even流水线指令，第二条指令是一条odd流水线指令，则它们都可以同时执行。 - First the architecture, instruction set design and timing and pipeline design of the soft IP are described in detail.
文中首先描述了该软核的体系结构，指令集设计，时序规划和流水线设计； - As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。 - In a general purpose DSP which is based on modified harvard architecture, a small instruction cache is adopted to alleviate the resource conflict in the pipeline.
在一款采用改进HARVARD总线结构的通用DSP中，通过设置一个小型指令CACHE来缓解流水线上的资源冲突。 - In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。 - The RISC MCU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-level instruction pipeline The performance of the RISC MCU has been improved by replacing micro-program with direct logic block.
设计的RISCMCU采用14位字长指令总线和8位字长数据总线分离的Harvard结构和二级指令流水设计，并使用硬布线逻辑代替微程序控制，加快了微控制器的速度，提高了指令执行效率。 - Design of the embedded DSPs 'architecture was described at this aspects: bus structure, instruction system, memory system, pipeline and addressing mode, etc.
本文就总线结构、指令系统、存储系统、流水线、寻址方式等几个方面对一个嵌入式DSP处理器μDSP的体系结构设计进行了详细的阐述。 - This paper introduces the principle of Cache, which is based on pipeline process technology, and how to apply its principle and technology to designing instruction Cache on the based of pipeline.
介绍了基于流水线技术的cache原理.并利用它的基本原理和技术，提出了设计指令cache关键技术和方法。 - The technical feature of new-generation RISC microprocessors is discussed in detail from the aspects of instruction pipeline, instruction scheduling, Cache design and multimedia supporting. The future of RISC microprocessors is also briefly addressed.
从流水线技术、指令调度技术、Cache设计技术及多媒体支持等方面详细讨论新一代RISC微处理器的技术特征，并简要论述RISC微处理器的发展趋向。 - The practical application shows that the instruction pipeline can decrease the designing complexity of the EPIC microprocessor effectively.
实际应用表明，指令控制流水线技术能够有效降低EPIC微处理器的设计复杂度。 - An Optimized Design of Instruction Cache based on Pipeline
一种基于流水线的指令CACHE优化设计 - Research on Instruction Parallelism-based Software Pipeline
基于指令并行的软件流水线研究 - So research on how to design a suitable and effectual instruction decoder can speedup the instruction decoding, enhance the efficiency of the instruction pipeline, and consequently improve the performance of microprocessor effectively.
设计高效合理的译码器是加快指令译码速度，提高指令流水效率，进而有效提高处理器性能的重要保证。 - The design was composed of five major parts: design instruction, general layout, process drawing, pipeline plane distribution drawing and main workshop equipments distribution chart.
设计由五大部分构成：设计说明书，工厂平面布置图，工艺流程图、车间管路平面布置图及主生产车间设备布置图。 - A RISC instruction pipeline architecture
一种RISC型微处理器指令流水线结构 - For architecture level ones, this paper introduces three kinds of optimization methods, which called operation optimization, instruction optimization and pipeline optimization.
在平台级优化方面，给出了操作优化、指令优化以及流水线优化等三种优化方法。 - For this purpose, the key point is the design of the instruction pipeline.
为了达到单周期实现的目的，其关键是指令流水线的设计。 - Through the system investigation for gas-liquid two-phase pipeline flow in this paper, the research would have some instruction significance for the design and management of multiphase flow pipeline. The study results could provide reference for the field work.
本文通过对气液两相管流的系统研究，对多相流管线的设计、管理等方面有一定的实用指导意义，研究结果对现场作业可提供参考。 - Test and performance analysis show that the dynamic instruction pipeline of the Godson 1 processor is efficient and its security design can effectively defense network attack based on buffer overflow technique.
测试表明龙芯1号处理器的指令流水线效率高，其安全设计能有效防范使用缓冲区溢出技术进行的网络攻击。 - Research and Implementation on Instruction Control Pipeline in General-Purpose EPIC Microprocessor
通用EPIC微处理器中指令控制流水线的研究与实现 - Brief instruction is given to principle of pipeline automatic welding in all positions, types and character of welding torch swing methods.
并简要介绍了管道全位置自动焊原理、焊枪摆动方式和特点。 - Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set ( program code), pipeline and storage.
结合ASIP体系结构特征，以应用特征为指导，针对指令集（程序代码）、流水线和存储部件进行了低功耗优化研究。 - The instruction control pipeline is specially designed for the instruction control module in the general-purpose EPIC microprocessor. The instruction control pipeline is used to carry the common or global information shared by all pipelines, and it employs the method of mutual locking with the computing pipelines.
指令控制流水线是在通用EPIC处理器内部专门为指令控制系统设计的一条与执行流水线相互锁步的流水线，用于携带共用信息和全局控制信息。 - This article introduce the principle of Digital Signal Processor, specially refer to basic concept and design technique, include: instruction set, pipeline, memory organization, hardware interface, adder, multiplier, clock strategy, test technique.
阐述了数字信号处理器的原理，重点介绍了设计数字信号处理器芯片的简单概念及设计方法，包括指令集、流水线、存储器组织、硬件接口、加法器、乘法器、时钟方案、测试接口等等。 - It then shows architecture design of instruction pipeline, including the double-shoot superscalar, the branch prediction and the dynamical execution.
然后，介绍指令流水线的结构设计，包括两路超标量结构，分支预测以及动态执行。 - This simulation platform is an instruction level emulator, using instruction queue to simulate the pipeline structure, and analog clock is adapted to simulate the clock cycle of performing an instruction.
该仿真平台是一个指令级仿真器，采用指令队列来模拟流水线结构，并且添加了模拟时钟来模拟每个指令在执行过程中所用的时钟周期。 - The instruction decoder is designed to facilitate prioritized thread scheduling. The instruction issue logic considers the utilization of the shared execution pipeline. And the interface between direct memory access and scratch-pad memory is refined.
设计了有利于线程优先级调度的译码段，考虑了共享流水线资源利用率的指令发射逻辑和改进的直接存储访问和便签式存储器接口。 - As another important component of the instruction unit, the interrupt can affect the performance of entire pipeline directly.
中断作为指令控制的重要组成部分，其性能的高低直接影响流水线的运行性能。 - A4-stage instruction pipeline for instruction execution makes at-speed test possible.
四级指令流水线的引入使全速测试成为可能。 - With the enhancement of environmental protection and civilization instruction consciousness in mind, trenchless technology which is used in underground pipeline laying project has been accepted gradually and developed greatly.
随着人们对环境保护和文明施工的日渐重视，非开挖地下管线铺设技术逐渐被人们所接受，并且取得了巨大发展。